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https://dblp.org/rec/journals/jcst/ZhangSC22

https://dblp.org/rdf/schema#authoredBy	https://dblp.org/pid/57/4707 + , https://dblp.org/pid/02/2264 + , https://dblp.org/pid/77/6336-1 +
https://dblp.org/rdf/schema#bibtexType	http://purl.org/net/nknouf/ns/bibtex#Article +
https://dblp.org/rdf/schema#documentPage	https://doi.org/10.1007/S11390-022-1499-9 +
https://dblp.org/rdf/schema#doi	https://doi.org/10.1007/S11390-022-1499-9 + , http://dx.doi.org/10.1007/S11390-022-1499-9 +
https://dblp.org/rdf/schema#listedOnTocPage	https://dblp.org/db/journals/jcst/jcst37 +
https://dblp.org/rdf/schema#numberOfCreators	3
https://dblp.org/rdf/schema#pagination	1290-1306
https://dblp.org/rdf/schema#primaryDocumentPage	https://doi.org/10.1007/S11390-022-1499-9 +
https://dblp.org/rdf/schema#publishedIn	J. Comput. Sci. Technol.
https://dblp.org/rdf/schema#publishedInJournal	J. Comput. Sci. Technol.
https://dblp.org/rdf/schema#publishedInJournalVolume	37
https://dblp.org/rdf/schema#publishedInJournalVolumeIssue	6
https://dblp.org/rdf/schema#title	TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis.
https://dblp.org/rdf/schema#yearOfPublication	2022
owl:sameAs	https://doi.org/10.1007/S11390-022-1499-9 + , http://dx.doi.org/10.1007/S11390-022-1499-9 +
rdf:type	https://dblp.org/rdf/schema#Publication + , https://dblp.org/rdf/schema#Article +
rdfs:label	Yi-Fan Zhang et al.: TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis. (2022)

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