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Https://dblp.org/rec/journals/ieiceee/LiCWLLZFHTS17
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https://dblp.org/rec/journals/ieiceee/LiCWLLZFHTS17
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https://dblp.org/rdf/schema#publishedIn IEICE Electron. Express
https://dblp.org/rdf/schema#publishedInJournal IEICE Electron. Express
https://dblp.org/rdf/schema#publishedInJournalVolume 14
https://dblp.org/rdf/schema#publishedInJournalVolumeIssue 2
https://dblp.org/rdf/schema#title Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration.
https://dblp.org/rdf/schema#yearOfPublication 2017
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rdfs:label Xiaoyun Li et al.: Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration. (2017)
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