| https://dblp.org/rdf/schema#authoredBy
|
https://dblp.org/pid/201/5763 +
, https://dblp.org/pid/65/4423 +
, https://dblp.org/pid/51/7450 +
, https://dblp.org/pid/18/4814 +
, https://dblp.org/pid/70/3994 +
|
| https://dblp.org/rdf/schema#bibtexType
|
http://purl.org/net/nknouf/ns/bibtex#Inproceedings +
|
| https://dblp.org/rdf/schema#createdBy
|
https://dblp.org/pid/201/5763 +
, https://dblp.org/pid/65/4423 +
, https://dblp.org/pid/51/7450 +
, https://dblp.org/pid/18/4814 +
, https://dblp.org/pid/70/3994 +
|
| https://dblp.org/rdf/schema#documentPage
|
https://doi.org/10.1109/VLSI-DAT.2017.7939659 +
|
| https://dblp.org/rdf/schema#doi
|
https://doi.org/10.1109/VLSI-DAT.2017.7939659 +
|
| https://dblp.org/rdf/schema#listedOnTocPage
|
https://dblp.org/db/conf/vlsi-dat/vlsi-dat2017 +
|
| https://dblp.org/rdf/schema#numberOfCreators
|
5
|
| https://dblp.org/rdf/schema#pagination
|
1-4
|
| https://dblp.org/rdf/schema#primaryDocumentPage
|
https://doi.org/10.1109/VLSI-DAT.2017.7939659 +
|
| https://dblp.org/rdf/schema#publishedAsPartOf
|
https://dblp.org/rec/conf/vlsi-dat/2017 +
|
| https://dblp.org/rdf/schema#publishedIn
|
VLSI-DAT
|
| https://dblp.org/rdf/schema#publishedInBook
|
VLSI-DAT
|
| https://dblp.org/rdf/schema#publishedInStream
|
https://dblp.org/streams/conf/vlsi-dat +
|
| https://dblp.org/rdf/schema#title
|
An analytical placer for heterogeneous FPGAs via rough-placed packing.
|
| https://dblp.org/rdf/schema#yearOfEvent
|
2017
|
| https://dblp.org/rdf/schema#yearOfPublication
|
2017
|
| owl:sameAs |
https://doi.org/10.1109/VLSI-DAT.2017.7939659 +
, http://dx.doi.org/10.1109/VLSI-DAT.2017.7939659 +
|
| rdf:type |
https://dblp.org/rdf/schema#Publication +
, https://dblp.org/rdf/schema#Inproceedings +
|
| rdfs:label |
Wan-Ning Wu et al.: An analytical placer for heterogeneous FPGAs via rough-placed packing. (2017)
|
