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https://dblp.org/pid/k/ManolisKatevenis +
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|
| https://dblp.org/rdf/schema#bibtexType
|
http://purl.org/net/nknouf/ns/bibtex#Inproceedings +
|
| https://dblp.org/rdf/schema#documentPage
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https://doi.org/10.1109/DSD.2016.106 +
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|
| https://dblp.org/rdf/schema#doi
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https://doi.org/10.1109/DSD.2016.106 +
, http://dx.doi.org/10.1109/DSD.2016.106 +
|
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https://dblp.org/db/conf/dsd/dsd2016 +
|
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27
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| https://dblp.org/rdf/schema#pagination
|
60-67
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| https://dblp.org/rdf/schema#primaryDocumentPage
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https://doi.org/10.1109/DSD.2016.106 +
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https://dblp.org/rec/conf/dsd/2016 +
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DSD
|
| https://dblp.org/rdf/schema#publishedInBook
|
DSD
|
| https://dblp.org/rdf/schema#title
|
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems.
|
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http://www.wikidata.org/entity/Q58746750 +
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2016
|
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2016
|
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https://doi.org/10.1109/DSD.2016.106 +
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https://dblp.org/rdf/schema#Publication +
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|
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Manolis Katevenis et al.: The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems. (2016)
|
