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Https://dblp.org/rec/conf/asicon/HuaWWLL15
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https://dblp.org/rec/conf/asicon/HuaWWLL15
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https://dblp.org/rdf/schema#title A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme.
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rdfs:label Siliang Hua et al.: A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme. (2015)
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